Archive | October, 2018

Can Multi-Core Processing Be Safe? Maybe … (CAST-32A)

3 Oct



Yes, you are busy and in today’s world you want immediate answers to important questions. “Is Multi-Core Processing safe?” The quick answer: “It can be, but …”. The slightly less quick answer: read the next few paragraphs. The proper answer: review CAST-32A or listen in on the free technical webinar on October 11, 2018 (sign up here: free but limited to the first 500 signups and these always are oversubscribed: Free Multi-Core Technical Webinar Signup: )

For safety-critical systems, a key facet of safety is “determinism”, via apriori planning, development, verification, then safety certification. But Multi-Core Processing (MCP) achieves faster processing by performing multiple activities at the same time, in parallel, by allocating tasks to different processing cores which are all embedded on a single processor. Today, your computer or cellphone likely uses MCP. Why MCP? Simple: we want our devices to do more and to do it more quickly. We’re slowly reaching the point of diminishing returns on silicon density technology where we’ve blissfully followed Moore’s law via improved processor fabrication and faster clock speeds. The answer: put multiple processing cores on a single chip and enable use of shared resources (memory, cache, etc.) to enable faster “parallel” processing (where actual “parallelism” is determined by both the application developer’s architecture and the task allocation model, including operating system).

But just as free lunches are rarely “free”, MCP isn’t fully “free”; certainly not for safety-critical systems where that pesky “Determinism” attribute is important. Just five years ago, MCP was considered to be so dangerous it was indirectly “banned” by worldwide aviation authorities. But those authorities are too smart (clever?) to actually “ban” a technology, so they published a document named CAST-32 which essentially stated “MCP could be used if the developer could prove all cores were disabled except for one”. Wait – if you disable all cores except one, then you don’t really “have” MCP, do you?!? Who knew the advanced certification experts had a great sense of humor. Now, when disabling three out of four engines on a four-engine airplane, you’re essentially flying a heavier single engine airplane with worse performance characteristics than a true single engine aircraft. Same with disabling all the cores on a multi-core processor. Brilliant.

And then, voila, technical evolution meets Today: the new update to CAST-32, aptly titled CAST-32A, allows for true MCP usage in airborne safety-critical systems. But the new MCP lunch isn’t free: we now have to prove determinism within the MCP including its innermost secret (intellectual property) workings. This means we must prove predictable memory and cache usage without interference. The burden of proof is on the user and typical users don’t understand (and don’t have access to) the real-time operating system (RTOS and MCP internal design to enable such proofs. Affirming MCP determinism is not trivial and you almost certainly need a certifiable MCP RTOS to enable MCP certifiability.

In the software certification world, there is an interesting relationship between OOT and MCP. Yes, both acronyms have three letters. But the real similarity is in utilizing safe subsets. Example: true C++ was not fully usable 15 years ago until rules for safe object oriented technology via defined language subsets (MISRA C++) were formalized. The result was that full C++ cannot be used without rules limiting its usage (for example, restricting the use of inheritance, polymorphism, overloading, and garbage collection). Similarly, full MCP usage will be difficult to prove deterministic usage so limitations simplify MCP acceptability; those limitations include core/task allocation models which greatly reduce potential interference paths between cores. So, a certifiable MCP use-case is there and becoming clearer. To make it very clear, simply watch the free AFuzion technical webinar at the link provided above. Or watch it anytime later via the AFuzion free technical training webinars posted on YouTube here: AFuzion Free Technical Youtube Webinars.

There you go: quick answers for you busy engineers. But we’re never too busy to be safe so keep your cores deterministic.

Safe Skies,

Cheers, Vance Hilderman (CEO AFuzion Inc.)